The Perseus receiver is a direct-sampling software-defined radio (SDR) receiver offering
continuous 10 kHz - 40 MHz coverage.
It features:
a 14 bit 80 MS/s analog/digital converter (ADC),
a high-performance FPGA-based digital down-converter (DDC),
a fast 480 Mbit/s USB2.0 PC interface,
which feed a baseband up to 1.6 MHz wide on the connected PC in I/Q format.
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The analog front end between the BNC antenna input and the ADC consists of a switched
attenuator (0 - 30 dB in 10 dB steps), a preselector with a bank of 10 switched filters
(9 BPF's for 1.7 - 40 MHz and 1 LPF for 0 - 1.7 MHz) and an RF preamplifier offering high
dynamic range to meet the most demanding amateur, SWL and radio-monitoring applications.
The front end, and the ADC clock source, are the only analog RF circuits in the Perseus.
The low-noise clock oscillator assures phase noise < -140 dBc/Hz at 10 kHz offset.
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Helmond
